32.3 Impact of Random Telegraph Signals on Vmin in 45nm SRAM

An alternating-bias random telegraph signal (RTS) characterization technique is presented, which shortens measurement time by 10x and also produces more accurate statistical distributions of RTS amplitudes. Measurements of RTS amplitudes in 45nm SRAM transistor Ids and cell write margin are reported and used to demonstrate a complex dependence of write margin on RTS in multiple transistors. Fail bit rate of SRAM with RTS is estimated using a statistical model populated by Iwrite measurements. Statistical analysis indicates a Vmin degradation of less than 50 mV due to RTS. INTRODUCTION Large temporal fluctuations of threshold voltage (Vth) in highly scaled CMOS transistors have been reported and attributed to random telegraph signals (RTS) [1, 2]. This paper presents a measurement technique for sampling worst-case Vth variation due to RTS. This technique is used to characterize RTS amplitude distributions in SRAM transistors of the 45nm technology. A padded-out SRAM cell array is utilized to extract RTS-induced fluctuations in SRAM write margin as well as to identify the transistors that contribute the most to write-margin fluctuation. Finally, a numerical method is developed to estimate Vmin degradation for write operation in large SRAM arrays. This method is validated using Vmin measurement data for a 64kb SRAM array. EXPERIMENTAL SETUP A 6T SRAM testchip is fabricated in an industrial 45nm CMOS process with 0.252μm bit-cells. The testchip contains four 64kb SRAM arrays as well as a macro with internal nodes of 160 cells padded out through a switch network (Fig. 1) [3]. Source-meters are used to access these internal nodes using precision 4-terminal Kelvin sensing methods to accurately set voltages at all nodes. RTS measurements are conducted at a sampling rate of 60 Hz. The SRAM array is used for measuring Vmin while the SRAM macro is used for measuring Ids and Iwrite. ALTERNATING-BIAS RTS MEASUREMENT TECHNIQUE RTS amplitude measurements are conventionally [1, 2] performed by measuring the drain current (Ids) of the transistor under a constant gate bias. Long measurement periods are required to observe RTS-related fluctuations caused by deep traps with long time constants. This makes it prohibitive to analyze a large population of transistors, to obtain statistics necessary for estimation of the properties of large SRAM arrays. A measurement technique is therefore introduced to accelerate the oxide trapping and de-trapping processes by 20x60 SRAM Macro (a) (b)